1. Field of the Invention
The present invention concerns a semiconductor device for home electronics or domestic equipments and for industrial use.
2. Description of the Related Art
A demand for higher functions has been increased year by year mainly for portable electronic equipments and, correspondingly, semiconductor devices of higher speed and higher capacity have been required. On the other hand, there is also a large requirement for decreasing the size of equipments and semiconductor packages capable of compatibilizing them have been developed. As an important technology for attaining the purpose, flip-chip mounting of connecting a semiconductor element by a protruding bump has been noted and they have already been used for various packages. The flip-chip mounting is a mounting system of connecting a chip having a bump formed on a pad onto an electrode of a substrate by a face-down method.
The flip-chip mounting system includes advantages, compared with an existent wire bonding connection system, that delay of signal transmission can be suppressed by shortening the connection length to enable high speed transmission and that reduction in the size is possible since the chip size is a package size. Predominant flip-chip mounting system includes, mainly, a solder bump connection system of connecting a chip and a substrate by a solder bump, an Au bump/solder connection system of forming a gold stud bump on the chip side and then connecting the stud bump and the wirings on the substrate with a solder, an ultrasonic connection method of forming a gold stud bump on the chip side and then connecting the stud bump and the wirings on the substrate by ultrasonic connection (refer to FIG. 7), and a contact connection system of forming a stud bump on the chip side and then connecting the stud bump and wirings on the substrate with a material mainly including a silver paste or a resin material such as ACF (Anisotropic Conductive Film).
On the other hand, a bump pitch has been made finer, and connection at 20 μm pitch has been announced for inter-chip connection of chip lamination package. While this is restricted at present only to the chip lamination package, it is expected that further refinement is conducted also on the connection between chip/substrate in the feature. Japanese Unexamined Patent Publication No. 2005-243714 and 2002-134541 describes a manufacturing method and a connection method of an electrode bump used for chip lamination which uses a structure of forming the bump top end so as to undergo larger stress change than that of the bump base portion, thereby causing buckling deformation to the bump top end to lower the stress upon connection.